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| www..com M2716 NMOS 16K (2K x 8) UV EPROM 2048 x 8 ORGANIZATION 525mW Max ACTIVE POWER, 132mW Max STANDBY POWER ACCESS TIME: - M2716-1 is 350ns - M2716 is 450ns SINGLE 5V SUPPLY VOLTAGE STATIC-NO CLOCKS REQUIRED INPUTS and OUTPUTS TTL COMPATIBLE DURING BOTH READ and PROGRAM MODES THREE-STATE OUTPUT with TIED-ORCAPABILITY EXTENDED TEMPERATURE RANGE PROGRAMMING VOLTAGE: 25V DESCRIPTION The M2716 is a 16,384 bit UV erasable and electrically programmable memory EPROM, ideally suited for applications where fast turn around and pattern experimentation are important requirements. The M2716 is housed in a 24 pin Window Ceramic Frit-Seal Dual-in-Line package. The transparent lid allows the user to expose the chip to ultraviolet light to erase the bit pattern. A new pattern can then be written to the device by following the programming procedure. 24 1 FDIP24W (F) Figure 1. Logic Diagram VCC VPP 11 A0-A10 8 Q0-Q7 EP G M2716 Table 1. Signal Names A0 - A10 Q0 - Q7 EP G VPP VCC VSS Address Inputs Data Outputs Chip Enable / Program Output Enable Program Supply Supply Voltage Ground VSS AI00784B July 1994 1/9 www..com M2716 Table 2. Absolute Maximum Ratings Symbol TA TBIAS TSTG VCC VIO VPP PD Parameter Ambient Operating Temperature Temperature Under Bias Storage Temperature Supply Voltage Input or Output Voltages Program Supply Power Dissipation grade 1 grade 6 grade 1 grade 6 Value 0 to 70 -40 to 85 -10 to 80 -50 to 95 -65 to 125 -0.3 to 6 -0.3 to 6 -0.3 to 26.5 1.5 Unit C C C V V V W Note: Except for the rating "Operating Temperature Range", stresses above those listed in the Table "Absolute Maximum Ratings" may cause permanent damage to the device. These are stress ratings only and operation of the device at these or any other conditions above those indicated in the Operating sections of this specification is not implied. Exposure to Absolute Maximum Rating conditions for extended periods may affect device reliability. Refer also to the SGS-THOMSON SURE Program and other relevant quality documents. Figure 2. DIP Pin Connections A7 A6 A5 A4 A3 A2 A1 A0 Q0 Q1 Q2 VSS 1 2 3 4 5 6 7 8 9 10 11 12 M2716 24 23 22 21 20 19 18 17 16 15 14 13 AI00785 VCC A8 A9 VPP G A10 EP Q7 Q6 Q5 Q4 Q3 DEVICE OPERATION The M2716 has 3 modes of operation in the normal system environment. These are shown in Table 3. Read Mode. The M2716 read operation requires that G = VIL, EP = VIL and that addresses A0-A10 have been stabilized. Valid data will appear on the output pins after time tAVQV, tGLQV or tELQV (see Switching Time Waveforms) dependingon which is limiting. Deselect Mode. The M2716 is deselected by making G = VIH. This mode is independent of EP and the condition of the addresses. The outputs are Hi-Z when G = VIH. This allows tied-OR of 2 or more M2716's for memory expansion. Standby Mode (Power Down). The M2716 may be powered down to the standby mode by making EP = VIH. This is independent of G and automatically puts the outputs in the Hi-Z state. The power is reduced to 25% (132 mW max) of the normal operating power. VCC and VPP must be maintained at 5V. Access time at power up remains either tAVQV or t ELQV (see Switching Time Waveforms). Programming The M2716 is shipped from SGS-THOMSON completely erased. All bits will be at "1" level (output high) in this initial state and after any full erasure. Table 3 shows the 3 programming modes. Program Mode. The M2716 is programmed by introducing "0"s into the desired locations. This is done 8 bits (a byte) at a time. Any individual address, sequential addresses, or addresses chosen at random may be programmed. Any or all of the 8 bits associated with an address location may be programmed with a single program pulse applied to the EP pin. All input voltage levels including the program pulse on chip enable are TTL compatible. The programming sequenceis: with VPP =25V, VCC = 5V, G = VIH and EP = VIL, an address is selected and the desired data word is applied to the output pins (VIL = "0" and VIH = "1" for both address and data). After the address and data signals are stable the program pin is pulsed from VIL to VIH with a 2/9 www..com M2716 DEVICE OPERATION (cont'd) pulse width between 45ms and 55ms. Multiple pulses are not needed but will not cause device damage. No pins should be left open. A high level (VIH or higher) must not be maintained longer than tPHPL (max) on the program pin during programming. M2716's may be programmed in parallel in this mode. Program Verify Mode. The programming of the M2716 may be verified either one byte at a time during the programming (as shown in Figure 6) or by reading all of the bytes out at the end of the programming sequence. This can be done with VPP = 25V or 5V in either case. VPP must be at 5V for all operating modes and can be maintained at 25V for all programming modes. Program Inhibit Mode. The program inhibit mode allows several M2716's to be programmed simultaneously with different data for each one by controlling which ones receive the program pulse. All similar inputs of the M2716 may be paralleled. Pulsing the program pin (from VIL to VIH) will program a unit while inhibiting the program pulse to a unit will keep it from being programmed and keeping G = VIH will put its outputs in the Hi-Z state. ERASURE OPERATION The M2716 is erased by exposure to high intensity ultraviolet light through the transparent window. This exposure discharges the floating gate to its initial state through induced photo current. It is recommended that the M2716 be kept out of direct sunlight. The UV content of sunlight may cause a partial erasure of some bits in a relatively short period of time. An ultraviolet source of 2537 A yielding a total integrated dosage of 15 watt-seconds/cm2 power rating is used. The M2716 to be erased should be placed 1 inch away from the lamp and no filters should be used. An erasure system should be calibrated periodically. The erasure time is increased by the square of the distance (if the distance is doubled the erasure time goes up by a factor of 4). Lamps lose intensity as they age, it is therefore important to periodically check that the UV system is in good order. This will ensure that the EPROMs are being completely erased. Incomplete erasure will cause symptoms that can be misleading. Programmers, components, and system designs have been erroneously suspected when incomplete erasure was the basic problem. Table 3. Operating Modes Mode Read Program Verify Program Inhibit Deselect Standby Note: X = VIH or VIL. EP VIL VIH Pulse VIL VIL X VIH G VIL VIH VIL VIH VIH X VPP VCC VPP VPP or VCC VPP VCC VCC Q0 - Q7 Data Out Data In Data Out Hi-Z Hi-Z Hi-Z 3/9 www..com M2716 AC MEASUREMENT CONDITIONS Input Rise and Fall Times Input Pulse Voltages Input and Output Timing Ref. Voltages 20ns 0.45V to 2.4V 0.8V to 2.0V Figure 4. AC Testing Load Circuit 1.3V 1N914 Note that Output Hi-Z is defined as the point where data is no longer driven. 3.3k Figure 3. AC Testing Input Output Waveforms 2.4V DEVICE UNDER TEST CL = 100pF OUT 2.0V 0.8V AI00827 0.45V CL includes JIG capacitance AI00828 Table 4. Capacitance (1) (TA = 25 C, f = 1 MHz ) Symbol C IN COUT Parameter Input Capacitance Output Capacitance Test Condition VIN = 0V VOUT = 0V Min Max 6 12 Unit pF pF Note: 1. Sampled only, not 100% tested. Table 5. Read Mode DC Characteristics (1) (TA = 0 to 70 C or -40 to 85 C; VCC = 5V 5% or 5V 10%; VPP = VCC) Symbol ILI ILO ICC ICC1 IPP VIL VIH VOL VOH Parameter Input Leakage Current Output Leakage Current Supply Current Supply Current (Standby) Program Current Input Low Voltage Input High Voltage Output Low Voltage Output High Voltage IOL = 2.1mA IOH = -400A 2.4 Test Condition 0 VIN VCC VOUT = VCC, EP = VCC EP = VIL, G = VIL EP = VIH, G = VIL VPP = VCC -0.1 2 Min Max 10 10 100 25 5 0.8 VCC + 1 0.45 Unit A A mA mA mA V V V V Note: 1. VCC must be applied simultaneously with or before VPP and removed simultaneously or after VPP. 4/9 www..com M2716 Table 6. Read Mode AC Characteristics (1) (TA = 0 to 70 C or -40 to 85 C; VCC = 5V 5% or 5V 10%; VPP = VCC) M2716 Symbol Alt Parameter Test Condition Min tAVQV tELQV tGLQV tEHQZ tGHQZ (2) (2) -1 Max 350 350 120 0 0 0 100 100 0 0 0 blank Min Max 450 450 120 100 100 Unit tACC tCE tOE tOD tDF tOH Address Valid to Output Valid Chip Enable Low to Output Valid Output Enable Low to Output Valid Chip Enable High to Output Hi-Z Output Enable High to Output Hi-Z Address Transition to Output Transition EP = VIL, G = VIL G = VIL EP = VIL G = VIL EP = VIL EP = VIL, G = VIL ns ns ns ns ns ns tAXQX Notes: 1. VCC must be applied simultaneously with or before VPP and removed simultaneously or after VPP. 2. Sampled only, not 100% tested. Figure 5. Read Mode AC Waveforms A0-A10 tAVQV EP tGLQV G tELQV Q0-Q7 VALID tAXQX tEHQZ tGHQZ Hi-Z DATA OUT AI00786 Table 7. Programming Mode DC Characteristics (1) (TA = 25 C; VCC = 5V 5%; VPP = 25V 1V) Symbol ILI ICC IPP IPP1 VIL VIH Parameter Input Leakage Current Supply Current Program Current Program Current Pulse Input Low Voltage Input High Voltage EP = VIH Pulse -0.1 2 Test Condition VIL VIN VIH Min Max 10 100 5 30 0.8 VCC + 1 Unit A mA mA mA V V Note: 1. VCC must be applied simultaneously with or before VPP and removed simultaneously or after VPP. 5/9 www..com M2716 Table 8. Programming Mode AC Characteristics (1) (TA = 25 C; VCC = 5V 5%; VPP = 25V 1V) Symbol tAVPH tQVPH tGHPH tPL1PL2 tPH1PH2 tPHPL tPLQX tPLGX tGLQV tGHQZ tPLAX Alt tAS tDS tOS tPR tPF tPW tDH tOH tOE tDF tAH Parameter Address Valid to Program High Input Valid to Program High Output Enable High to Program High Program Pulse Rise Time Program Pulse Fall Time Program Pulse Width Program Low to Input Transition Program Low to Output Enable Transition Output Enable to Output Valid Output Enable High to Output Hi-Z Program Low to Address Transition EP = VIL 0 2 Test Condition G = VIH G = VIH Min 2 2 2 5 5 45 2 2 120 100 55 Max Units s s s ns ns ms s s ns ns s Notes: 1. VCC must be applied simultaneously with or before VPP and removed simultaneously or after VPP. 2. Sampled only, not 100% tested. Figure 6. Programming and Verify Modes AC Waveforms A0-A10 tAVPH Q0-Q7 tQVPH DATA IN VALID tPLAX DATA OUT tPLQX tPLGX G tGHPH EP tPHPL PROGRAM VERIFY AI00787 tGLQV tGHQZ 6/9 www..com M2716 ORDERING INFORMATION SCHEME Example: M2716 -1 F 1 Speed and VCC Tolerance -1 blank 350 ns, 5V 10% 450 ns, 5V 5% F Package FDIP24W Temperature Range 1 6 0 to 70 C -40 to 85 C For a list of available options (Speed, VCC Tolerance, Package, etc...) refer to the current Memory Shortform catalogue. For further information on any aspect of this device, please contact SGS-THOMSON Sales Office nearest to you. 7/9 www..com M2716 FDIP24W - 24 pin Ceramic Frit-seal DIP, with window Symb Typ A A1 A2 B B1 C D E E1 e1 e3 eA L S N FDIP24W mm Min Max 5.71 0.50 3.90 0.40 1.17 0.22 1.78 5.08 0.55 1.42 0.31 32.30 15.40 13.05 2.54 27.94 - - 16.17 3.18 1.52 7.11 - 4 24 15.80 13.36 - - 18.32 4.10 2.49 - 15 0.280 0.100 1.100 Typ inches Min Max 0.225 0.020 0.154 0.016 0.046 0.009 0.070 0.200 0.022 0.056 0.012 1.272 0.606 0.514 - - 0.637 0.125 0.060 - 4 24 0.622 0.526 - - 0.721 0.161 0.098 - 15 A2 A1 B1 B e3 D S N 1 A L eA C e1 E1 E FDIPW-a Drawing is not to scale 8/9 www..com M2716 Information furnished is believed to be accurate and reliable. However, SGS-THOMSON Microelectronics assumes no responsibility for the consequences of use of such information nor for any infringement of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of SGS-THOMSON Microelectronics. Specifications mentioned in this publication are subject to change without notice. This publication supersedes and replaces all information previously supplied. SGS-THOMSON Microelectronics products are not authorized for use as critical components in life support devices or systems without express written approval of SGS-THOMSON Microelectronics. (c) 1994 SGS-THOMSON Microelectronics - All Rights Reserved SGS-THOMSON Microelectronics GROUP OF COMPANIES Australia - Brazil - China - France - Germany - Hong Kong - Italy - Japan - Korea - Malaysia - Malta - Morocco - The Netherlands Singapore - Spain - Sweden - Switzerland - Taiwan - Thailand - United Kingdom - U.S.A. 9/9 |
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